1. Technical Field
The present disclosure relates to a row decoder for non-volatile memory devices, in particular of the phase-change type, to which the following treatment will make particular reference, without this implying any loss of generality.
2. Description of the Related Art
Non-volatile phase-change memories (PCMs) are known, in which, for storing information, the characteristics of materials that have the property of switching between phases having different electrical characteristics are exploited. For example, these materials can switch between a disorderly amorphous phase and an orderly crystalline or polycrystalline phase, and the two phases are associated to resistivity of considerably different values, and consequently to a different value of a stored datum. For example, the elements of the Group VI of the periodic table, such as tellurium (Te), selenium (Se), or antimonium (Sb), referred to as chalcogenides or chalcogenic materials, can advantageously be used for producing phase-change memory cells. The phase changes are obtained by increasing locally the temperature of the cells of chalcogenic material, through resistive electrodes (generally known as heaters) set in contact with respective regions of chalcogenic material. Selection devices (for example, MOSFETs), are connected to the heaters, and enable the passage of a programming electrical current through a respective heater; this electrical current, by the Joule effect, generates the temperatures for the phase change. During reading, the state of the chalcogenic material is detected by applying a voltage that is sufficiently low as not to cause a marked heating, and then by reading the value of the current flowing in the cell. Given that the current is proportional to the conductivity of the chalcogenic material, it is possible to determine in which state the material is, and then determine to the data stored in the memory cells.
In a known manner, non-volatile memories include an array of memory cells organized in rows (wordlines) and columns (bitlines). Each memory cell is formed, in the case of PCMs, by a phase-change storage element and by a selector transistor, connected in series. In particular, a wordline is defined by the set of all the control terminals of the selector transistors aligned along one and the same row.
A column decoder and a row decoder, based on logic address signals received at their input and more or less complex decoding schemes, enable selection of the memory cells, and in particular of the corresponding wordlines and bitlines each time addressed, enabling biasing thereof to appropriate voltage and current values by corresponding biasing stages.
In the specific case of PCMs, it should be noted that the reading operations employ, as compared to the programming operations, values sensibly lower of the biasing voltage applied to the wordlines, especially if selector transistors of a MOS type are used (for example, 1.2 V in reading and 2.5 V in programming).
A memory array of PCM elements requires a significant static power for biasing the control terminals of the selector transistors connected to the selected row during a program pulse (much lower on gate terminals, in the case of MOS transistors, and higher on base terminals, in the case of bipolar transistors). Accordingly, it is clear that it is advantageous to reduce the number of storage elements (and associated selector transistors) connected to one and the same row. However, given that the row decoder requires a high area occupation, it is necessary to reach a compromise between the static power required in the row selection and the efficiency in the area occupation of the non-volatile memory device.
In the last few years, the use has been proposed, for non-volatile memory devices of a flash type, of a hierarchical row-decoding architecture. In general, even though many different embodiments have been presented, a hierarchical decoding is based on the use of at least two hierarchical row-decoding levels: a global level and a local level. The hierarchical architecture envisages the presence of global wordlines and of a plurality of local wordlines for each global wordline. A global row decoder addresses the global wordlines (i.e., it selects the global wordlines and biases the global wordlines each time selected), whilst each local row decoder addresses the local wordlines, and in particular enables connection between the addressed local wordline and the respective global wordline, enabling biasing of the wordlines of the memory array physically connected to the local wordlines.
For example, U.S. Pat. No. 6,233,198 discloses a high-density flash memory device using a hierarchical row-decoding architecture.
Even though this decoding architecture enables, as compared to traditional solutions, an improved compromise to be reached between the dynamic power used for biasing the selected wordlines and the area occupation of the row decoder, the power consumption levels still constitute an important design limitation, especially in the case of phase-change non-volatile memory devices.